1. Field of the Invention
The present invention generally relates to a data transfer device, image processing apparatus, data transferring program, and recording medium, and more specifically, a data transfer device, an image processing apparatus, a data transferring program, and a recording medium including a serial interface for communicating via plural transmission paths.
2. Description of the Related Art
In image forming apparatuses such as a copier, a facsimile machine, a printer, and a multifunction peripheral, image data for main scanning lines are required to be transferred from an image processing unit to an image forming unit and when the transferred data are not transferred on time an image formed by the image forming unit may become abnormal.
Recently, example image forming apparatuses carry out various data processing under a control of a Central Processing Unit (CPU) of a semiconductor integrated circuit such as an Application Specific Integrated Circuit (ASIC) having plural functional modules installed in the image forming apparatus, and a Peripheral Component Interconnect Express (PCI) express being a high speed split transaction bus which can issue a request without waiting for a response which is separated from the requests is used.
In this PCI Express, the link width and the data rate (2.5 GT/s or 5.0 GT/s) are designed so that the data transfer does not become imperfect even if the maximum frequency band is required for presumed data transfers.
In second generation standard called Gen2 of the PCI Express, it is possible to select one of operating frequencies 2.5 GT/s and 5.0 GT/s of a transmission path or change a link width after a link-up. Under this standard, there are permitted link widths of ×1, ×2, ×4, ×8, ×12, ×16, and ×32.
A transmission path connected by the PCI Express in point-to-point connects devices located on both ends of the transmission path in a protocol hierarchy of the data link layer and lower without interposing software. A connection between the devices on the both ends of the PCI Express is established with the maximum link width among the link widths usable by the devices.
However, the transmission path using the PCI Express is constantly operated in the installed link width and operating frequency. Therefore, in cases other than a case where the greatest frequency band is required, the transmission path is operated with redundant link width and operating frequencies thereby causing useless power consumption. Especially, the PHY of the PCI Express is operated at a very high rate (2.5 GHz/5 GHz) in comparison with the operating frequency (about 100 MHz) inside the ASIC. Because the power consumption is proportional to the frequency, the operating condition largely effects on the power consumption.
For example, when the PCI Express is set such that the link width is ×4 and the operating frequency is 5 GT/s, the PCI Express is operated under the link width of ×4 and the operating frequency of 5 GT/s even if a data transfer does not require the frequency band such as a simple data access.
As described, it is unavoidable to increase the number of lanes more and make the operating frequency higher as the speed of the image forming apparatus increases more. Therefore, the reduction of the power consumption of circuits related to the PCI Express has great importance in reducing the power consumption of the entire image forming apparatus.
Therefore, there is proposed, in Patent Document 1, a technique that the electrical power is saved by changing an interface with a reading unit in an electrical power saving mode until there arrives a read command from the reading unit. After applying the Patent Document 1 to the PCI Express, it is possible to save energy in an idle state in which a data transfer is not carried out.
However, in Patent Document 1, the interface is set to the idle state causing no data transfer and the link width and the operating frequency are not considered. Therefore, even when data transfer is sufficiently possible while the data transfer is generating, the device on the both ends of the PCI Express has the maximum link width and the connection if established at the maximum operating frequency. Therefore, further electrical power saving is possible.
In the PCI Express of the second generation standard, it is possible to select the data rate of 2.5 GT/s or 5.0 GT/s of the transmission path and change the link width by setting a configuration register. When the register is set by a software control, a processing time of software necessary for the Configuration register becomes relatively large in comparison with an operating time of hardware and it does not processes in real time. Therefore, data transmission may be troubled.
Patent Document 1: Japanese Laid-Open Patent Application No. 2009-176294